The present invention will be described with an example application for an Ethernet computer network peripheral device which couples a host computer system to a network of computers. In this example application, a CPU of the host computer system and the Ethernet computer network peripheral device share access to a shared memory within the host computer system. In particular, the present invention is described with respect to buffers that are shared for access between the CPU and the computer network peripheral device as described herein. However, from this example application, it should be appreciated by one of ordinary skill in the art of electronic systems that the present invention may be practiced for other computer peripheral devices that share access to any shared memory with the host computer system.
Referring to FIG. 1, a computer peripheral device 102 may be an Ethernet computer network peripheral device which allows a host computer 104 to communicate with other computers within a network of computers 106. Such a computer peripheral device 102 receives and transmits data packets on the network of computers 106. The computer peripheral device 102, which may be an Ethernet computer network peripheral device, receives and transmits data packets on the network of computers 106 in accordance with standard data communications protocols such as the IEEE 802.3 network standard or the DIX Ethernet standard as is commonly known to one of ordinary skill in the art of Ethernet computer network peripheral device design.
The host computer 104 may be a PC or any other type of computer, and has a host system which includes a CPU 108 and a shared memory 110 which may be any data storage device found in a PC or a workstation. The CPU 108 further processes a data packet received from the network of computers 106 or generates a data packet to be transmitted on the network of computers 106. The shared memory 110 is shared between the CPU 108 of the host system 104 and the computer network peripheral device 102. In a DMA (Direct Memory Access) mode of operation, the computer network peripheral device 102 has direct access to the shared memory 110 within the host system of the computer 104.
When the computer network peripheral device 102 receives a data packet from the network of computers 106, that data packet is written into at least one buffer within the shared memory 110 directly by the computer network peripheral device 102 for further processing by the host system CPU 108. The CPU 108 also accesses those buffers within the shared memory 110 to further process the data packet stored within the shared memory 110.
Alternatively, the CPU 108 accesses at least one buffer within the shared memory 110 to write a data packet to be transmitted on the network of computers 106. The computer network peripheral device 102 then accesses those buffers within the shared memory 110 to read the stored data packet in order to transmit such a data packet over the network of computers 106.
Since both the CPU 108 and the computer network peripheral device 102 access the shared memory 110, such shared access to the shared memory 110 is coordinated between the CPU 108 and the computer network peripheral device 102 for harmonious interaction between the two devices. Thus, referring to FIG. 2, the CPU 108 of the host system 104 and the computer peripheral device 102 share a first buffer 212, a second buffer 214, and a third buffer 216 in the shared memory 110. A buffer may be used to store a data packet or a portion of a data packet received or to be transmitted over the network of computers 106.
Access to the shared memory 110 between the CPU 108 and the computer network peripheral device 102 is coordinated by the use of descriptors. Referring to FIG. 2, each buffer within the shared memory 110 has a respective descriptor. A first descriptor 222 corresponds to the first buffer 212, a second descriptor 224 corresponds to the second buffer 214, and a third descriptor 226 corresponds to the third buffer 216. Each descriptor has respective control data and respective status data corresponding to the respective buffer associated with that descriptor.
Thus, the first descriptor 222 has first control data 232 and first status data 242 corresponding to the first buffer 212. The second descriptor 224 has second control data 234 and second status data 244 corresponding to the second buffer 214. The third descriptor 226 has third control data 236 and third status data 246 corresponding to the third buffer 216.
The CPU 108 writes the control data corresponding to a descriptor to communicate control information to the peripheral device 102, including the state of processing by the CPU 108 data within the corresponding buffer. Thus, the peripheral device 102 reads the control data corresponding to a descriptor to determine the state of processing by the CPU 108 data within that corresponding buffer. On the other hand, the peripheral device 102 writes the status data corresponding to a descriptor to communicate status information to the CPU 108, including the state of processing by the peripheral device 102 data within the corresponding buffer. Thus, the CPU 108 reads the status data corresponding to a descriptor to determine the state of processing by the peripheral device 102 data within that corresponding buffer.
In the design of some computer peripheral devices, the control block and the status block, corresponding to a given buffer, are stored into separate independent locations in memory. A first location in memory of the control block cannot be determined from the second location in memory of the status block, and vice versa (i.e., the second location in memory of the status block cannot be determined from the first location in memory of the control block). An example of such a design is to minimize cache data processing overhead as described in a copending patent application with title "Minimizing Cache Overhead by Storing Data for Communications between a Peripheral Device and a Host System into Separate Locations in Memory," to Robert Williams having Ser. No. 09/204,978 and filing date of Dec. 3, 1998, and having common assignee herewith. This patent application is incorporated herein by reference.
When the control block and the status block, corresponding to a given buffer, are stored into separate independent locations in memory, the manner in which the CPU 108 writes control data and in which the computer peripheral device 102 writes the status data may affect the data processing overhead of the CPU 108 or the computer peripheral device 102.